1. Field of the Invention
The present invention relates to a timing controller, an image display device using the same, a timing signal generating method, and an image display control method, and more particularly to the timing controller in which a method for generating a start pulse to be used for a driving of a scanning line and a signal line, the image display device using the same, the timing signal generating method, and the image display control method.
2. Description of the Related Art
Conventionally, an image display device is widely used in various fields. There are different types of usage modes of the image display device. For example, when the image display device is disposed in an upward location for working, it is necessary, structurally, that the image display device can be inverted up and down. In some cases, the image display device has to be turned upside down so that visibility of a viewer is improved. Also, it is preferable that a video image inverted right and left is displayed on a screen in an image display device provided at a barbershop, a hair salon or a like, such that a customer can see, without feeling abnormal, a video image through a front mirror, that is, a video image in a front mirror. To implement these functions, conventionally, there is a display device such as a TV (television), monitor, or the like having a function of inverting a display screen right and left or up and down.
A related display device is known which can perform not only sequential scanning but also reverse scanning in upward and downward directions or in right and left directions in particular. In the related display device described above, a timing controller 210 for the display device as shown in FIG. 10 is used.
The timing controller 210 for the display device includes a VSP generating section 214 to generate a VSP (Vertical Start Pulse) signal at a time designed in advance based on a combination between a count of outputs from a scanning line driving IC (Integrated Circuit) to be determined at a setting terminal and also based on resolution of a display panel to be determined at the setting terminal and a scanning direction, a timing signal generating signal to generate an HSP (Horizontal Start Pulse) signal for a signal line driving IC, a DLP (Data Latch Pulse) signal, a VCK (Vertical Clock) signal for the scanning line driving IC, a VOE (Vertical Output Enable) signal, a POL (Polarity inverting) signal to AC (Alternating Current)-drive a liquid crystal display, and a DCK (Dot Clock) signal, and a video data processing section to process video data to be supplied from the outside.
FIG. 11 shows a related liquid crystal display device 200 constructed by using the above timing controller 210 for a display device. The liquid crystal display device 200 is made up of a timing controller 210 for a display device, a liquid crystal display panel 220, a signal line electrode driving circuit 230, and a scanning line electrode driving circuit 240.
The liquid crystal display panel 220 includes a plurality of scanning electrodes mounted on its substrate at a predetermined interval in a row direction, a plurality of signal line electrodes mounted on its substrate at a predetermined interval in a column direction, a liquid crystal cell being an equivalently capacitive load at an intersection for both the electrodes in a manner opposite and being sandwiched, a common electrode, a TFT (Thin Film Transistor) to drive a corresponding liquid crystal cell, and a capacitor to store electric charges corresponding to data for one vertical synchronizing period.
The signal line electrode driving circuit 230 is made up of one or more HTCPs (Horizontal Tape Carrier Packages) 231 each having a signal line driving IC 232 and having a plural-stage structure in which the signal line driving ICs 232 are serially connected thereto. Each of the signal line driving ICs 232 captures image data with timing when each of the HSP, DLP, POL and DCK signals is outputted from the timing controller 210 for the display device and has a function of converting the image into a corresponding voltage for every pixel of one line to apply the converted voltage to a corresponding pixel electrode of one line through a drain electrode of the TFT (not shown).
The scanning line electrode driving circuit 240 is made up of one or more VTCPs (Vertical Tape Carrier Packages) 241 each having a scanning line driving IC 242 to be used for driving scanning lines of the liquid crystal display panel 220. The scanning line driving IC 242, based on the VSP, VOE, and VCK signals to be outputted from the timing controller 210 for the display device, performs an operation to simultaneously control all the scanning line electrodes of the TFT belonging to the line for every line sequentially from above in synchronization with a VCK signal and brings each TFT of the line being now controlled into conduction and applies a gray level voltage to be supplied to the signal line connected, at the time of being conducted, from the signal line driving IC 32 to its output, to the pixel electrode of a corresponding liquid crystal cell.
The scanning line driving IC 242, as shown in FIG. 12, is made up of a shift register section 2421 and a scanning line outputting section 2422. The shift register section 2421 sequentially performs a shifting operation in accordance with the vertical start pulse signals VSP1 and VSP2 for the scanning line driving IC 242 to be supplied from the timing controller 210, clock signal VCK for the scanning line driving IC 242, and a signal of an RL terminal to be set by the shift register determining a scanning direction, at a time of rising of the VCK signal for the scanning line driving IC 242. The scanning line outputting section 2422 performs a shift operation on its signal level from an internal operating level to an outputting level. The scanning line electrode driving circuit 240 sequentially generates a scanning signal by its scanning line driving IC 242 and sequentially applies the generated scanning signal to a corresponding scanning electrode of the liquid crystal display panel 220.
In general, the count of lines for resolution of the liquid crystal display panel 220 is larger than the count of outputs from the scanning line driving IC 242. Therefore, a plurality of scanning line driving ICs 242 is cascade-connected. For example, in a case of XGA (eXtended Graphics Array) resolution, since its resolution is 768 lines, as shown in FIG. 13, three pieces of the scanning line driving ICs 242 providing 256 outputs are used to drive the liquid crystal display panel 220. In this case, in the scanning line driving IC 242, the VSP2 terminal of the scanning line driving IC 242(1) is cascade-connected to the VSP1 terminal of the scanning line driving IC 242(2) and the VSP2 terminal of the scanning line driving IC 242(2) is cascade-connected to the VSP1 terminal of the scanning line driving IC 242(3).
As shown on page 2 and page 3 in Patent Reference 1, at a time of sequential scanning, setting is made so that RL=“low” and the VSP2 output signal from the scanning line driving IC 242(1) becomes a VSP1 input signal to the scanning line driving IC 242(2) and a shift operation is performed for driving of scanning lines after 257 lines without timing discontinuation. Moreover, in a similar manner, the VSP2 output signal from the scanning line driving IC 242(2) becomes the VSP1 input signal to the scanning line driving IC 242(3) and a shift operation is performed for driving of scanning lines after 513 lines without timing discontinuation.
Further, at a time of reverse scanning, setting is made so that RL=“High” and the VSP2 output signal from the scanning line driving IC 242(3) becomes the VSP2 input signal to the scanning line driving IC 242(2) and a shift operation is performed for driving of scanning lines after 257 lines without timing discontinuation. Moreover, in a similar manner, the VSP2 output signal from the scanning line driving IC 242(2) becomes the VSP1 input signal to the scanning line driving IC 242(1) and a shift operation is performed for driving of scanning lines after 513 lines without timing discontinuation.
On the other hand, in recent years, there is increasing a demand for lowering the price of a liquid crystal display device and, to satisfy this demand, the reduction in costs for component materials is becoming a serious problem. In order to respond to the problem, an effort is being made to give priority to costs for a scanning line driving IC making up one of the component parts. For example, the case of using the scanning line driving IC providing not 256 outputs but low-priced 300 outputs is increasing. For example, when a scanning line electrode driving circuit having its XGA of 768 lines is constructed by using three scanning line driving ICs providing 300 outputs each, if the same connecting method for the scanning line driving ICs is the same as that in FIG. 13, as shown in FIG. 14, the excessive outputs of 132 from the scanning line driving ICs occur.
The 132 extra outputs are not connected to the liquid crystal display panel 220 and, as a result, in ordinary cases, open processing is performed and the 132 extra outputs become dummy outputs. In this case, these excessive outputs do not create problems in the sequential scanning, however, the 132 extra outputs become problems in the reverse scanning in upward and downward directions.
That is, in the reverse scanning in the upward and downward directions, as shown in FIG. 14, the driving for scanning starts sequentially from O300 of the scanning line driving IC 242(3) and the initial 300 excessive outputs are dummy outputs and, therefore, are not connected to the liquid crystal display panel 220. As a result, the 132 outputs are not shown and are abnormally displayed in a state of being deviated by 132 lines in the upward and downward directions, still leaving unsolved technical problems in the above related technology.
Due to shared use of cost-reduced components, shared use of materials or members for the timing controller being one of its components is increasing and one timing controller can respond to a plurality of resolutions and a plurality of numbers of outputs from the scanning line driving IC. However, in the above configuration, at the time of designing the timing controller at the development stage, the excessive outputs from the scanning line driving IC are calculated by combinations of resolution at which an image is displayed by one or more resolution setting terminal and of the count of outputs from the scanning line driving IC to be set by the output number setting terminal of one or more scanning line driving ICs and the timing of the VSP2 signal for the scanning line driving IC at the time of reverse scanning is calculated and designed. However, the designed value has to be embedded as a fixed value by combining various resolutions with the count of outputs from various scanning line driving ICs at the time of developing the timing controller.
For example, when the timing controller is so configured as to correspond to both the resolutions XGA (1024×768) and VGA (640×480) and to the count of outputs from the scanning line driving IC of both 256 channels and 300 channels,
if three 256 output drivers are used for the XGA (768 lines) resolution, excessive outputs from the driver are 0,
if three 256 output drivers are used for XGA (768 lines) resolution, excessive outputs from the driver are 132,
if two 256 output drivers are used for XGA (480 lines) resolution, excessive outputs from the driver are 32, and
if two 300 output drivers are used for VGA (480 lines) resolution, excessive outputs from the driver are 120.
It is necessary to control the timing controller so that the VSP signals for the scanning line driving IC at the time of reverse scanning achieved by these combinations are outputted with timing of 0, 132, 32, and 120.
A method is disclosed in Patent Reference 2 in which a difference between the count of scanning lines and the count of scanning channels is calculated and a clock signal containing a dummy clock is generated based on the difference and is then inserted into periods of the VCK.
As described above, when the scanning line electrode driving circuit is constructed at a plural stage in which the scanning line driving ICs are serially connected, if the total count of outputs of each of the entire scanning line driving IC are consistent with the count of lines at predetermined resolution of a liquid crystal display panel, no problems arises in displaying. However, in the liquid crystal display device constructed by using a related timing controller, when an excessive output from the scanning line driving IC occurs, in the reverse operations, as measures to be taken against the occurrence of the excessive output, there is no way but to use the value determined by combining the resolution at the time of designing the timing controller with the count of outputs from the scanning line driving IC. The reason is that the combination of the resolution and the count of outputs from the scanning line driving IC is determined in advance at the time of designing.
That is, when the timing controller is driven in accordance with the combination assumed at the time of designing, if an excessive output from the scanning line driving IC occurs, it is necessary that the assumed resolution and the count of outputs from the scanning line driving IC are set to the value already set at the time of designing and, when other resolution and combination are used, a constant for the signal processing board must be again set on the signal processing board, which causes common designing of the signal processing board to be lacking in flexibility.
Moreover, it is impossible to use a scanning line driving IC other than assumed at the time of development and designing of its original one in a shared manner, which causes a difficulty in shared use of other IC parts or other timing controllers, thus resulting in a hindrance to a reduction in costs.
Since there is a limitation to the count of outer setting terminals used to determine the resolution of a timing controller or to the count of outer terminals used to determine the count of outputs from the scanning line driving IC, it is necessary to select, depending on the development state or technological trends at the time of the development, the corresponding resolution or the count of outputs from the scanning line driving IC and the timing of outputting the VSP2 signal was determined by the combination of each resolution or the count of outputs from the already-existing scanning line driving IC. Therefore, when a reduction of costs and shared use of other products is to be achieved by using a new timing controller, unless the new timing controller is constructed so as to correspond to the count of outputs from the already-existing scanning line driving IC, the new timing controller cannot be used as a device for reducing costs and for shared use.
Further, the problem of this kind can be partially solved by using the method stated in Patent Reference 2. However, the disclosed technology also has a problem. In this disclosed method, display resolution and count of outputs from the scanning line driving IC have to be combined in advance at a time of development of the timing controller. As a result, another problem arises that normal operation is not performed if the combination is made by using a different resolution and a count of a different output from the scanning line driving IC. Furthermore, a complicated circuit for inserting a dummy clock among clocks is required.